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rev. e information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a op249 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 dual, precision jfet high-speed operational amplifier pin connections 8-lead cerdip (z suffix), 8-lead plastic mini-dip (p suffix) 1 2 3 4 8 7 6 5 a b ++ +in a v +in b ?n b ?n a out a v+ out b 8-lead so (s suffix) 1 2 3 4 8 7 6 5 a b + + +in a v +in b in b in a out a v+ out b features fast slew rate: 22 v/ s typ settling time (0.01%): 1.2 s max offset voltage: 300 v max high open-loop gain: 1000 v/mv min low total harmonic distortion: 0.002% typ improved replacement for ad712, lt1057, op215, tl072, and mc34082 applications output amplifier for fast d/as signal processing instrumentation amplifiers fast sample/holds active filters low distortion audio amplifiers input buffer for a/d converters servo controllers general description the op249 is a high speed, precision dual jfet op amp, simi- lar to the popular single op amp, the op42. the op249 outper- forms available dual amplifiers by providing superior speed with excellent dc performance. ultrahigh open-loop gain (1 kv/mv minimum), low offset voltage, and superb gain linearity makes the op249 the industrys first true precision, dual high speed amplifier. with a slew rate of 22 v/ s typical and a fast settling time of less than 1.2 s maximum to 0.01%, the op249 is an ideal choice for high speed bipolar d/a and a/d converter applications. the excellent dc performance of the op249 allows the full accuracy of high resolution cmos d/as to be realized. symmetrical slew rate, even when driving large load, such as, 600 ? or 200 pf of capacitance and ultralow distortion, make the op249 ideal for professional audio applications, active filters, high speed integrators, servo systems, and buffer amplifiers. the op249 provides significant performance upgrades to the tl072, ad712, op215, mc34082, and the lt1057. 10 0% 100 90 500ns 10mv 870ns figure 1. fast settling (0.01%) 0.010 0.001 20 10k 100 1k 20k t a = 25 c v s = 15v v o = 10v p-p r l = 10k a v = 1 figure 2. low distortion a v = 1, r l = 10 k ? 10 0% 100 90 1s 5v figure 3. excellent output drive, r l = 600 ?
C2C rev. e op249?pecifications electrical characteristics op249a op249f parameter symbol conditions min typ max min typ max unit offset voltage v os 0.2 0.5 0.2 0.7 mv long term offset voltage v os (note 1) 0.8 1.0 mv offset stability 1.5 1.5 v/month input bias current i b v cm = 0 v, t j = 25 c 30 75 3075pa input offset current i os v cm = 0 v, t j = 25 c625 625pa input voltage range ivr (note 2) 12.5 12.5 v 11 11 v C12.5 C12.5 v common-mode rejection cmr v cm = 11 v 80 90 80 90 db power-supply rejection ratio psrr v s = 4.5 v to 18 v 12 31.6 12 50 v/v large-signal voltage gain a vo v o = 10 v, r l = 2 k ? 1000 1400 500 1200 v/mv output voltage swing v o r l = 2 k ? 12.5 12.5 v 12.0 12.0 v C12.5 C12.5 v short-circuit current limit i sc output shorted to 36 36 ma ground 20 50 20 50 ma C33 C33 ma supply current i sy no load, v o = 0 v 5.6 7.0 5.6 7.0 ma slew rate sr r l = 2 k ? , c l = 50 pf 18 22 18 22 v/ s gain-bandwidth product gbw (note 3) 3.5 4.7 3.5 4.7 mhz settling time t s 10 v step 0.01% 4 0.9 1.2 0.9 1.2 s phase margin 0 0 db gain 55 55 degrees differential input impedance z in 10 12 610 12 6 ? pf open-loop output resistance r o 35 35 ? voltage noise e n p-p 0.1 hz to 10 hz 2 2 v p-p voltage noise density e n f o = 10 hz 75 75 nv/ hz f o = 100 hz 26 26 nv/ hz f o = 1 khz 17 17 nv/ hz f o = 10 khz 16 16 nv/ hz current noise density i n f o = 1 khz 0.003 0.003 pa/ hz voltage supply range v s 4.5 15 18 4.5 15 18 v notes 1 long-term offset voltage is guaranteed by a 1000 hr life test performed on three independent wafer lots at 125 c with ltpd of three. 2 guaranteed by cmr test. 3 guaranteed by design. 4 settling time is sample tested. specifications subject to change without notice. electrical characteristics op249g parameter symbol conditions min typ max unit offset voltage v os 0.4 2.0 mv input bias current i b v cm = 0 v, t j = 25 c4075pa input offset current i os v cm = 0 v, t j = 25 c1025pa input voltage range ivr (note 1) 12.5 v 11 v C12.0 v common-mode rejection cmr v cm = 11 v 76 90 db power supply rejection ratio psrr v s = 4.5 v to 18 v 12 50 v/v large signal voltage gain a vo v o = 10 v; r l = 2 k ? 500 1100 v/mv output voltage swing v o r l = 2 k ? 12.5 v 12.0 v C12.5 v short-circuit current limit i sc output shorted to ground 36 ma 20 50 ma C33 ma supply current i sy no load; v o = 0 v 5.6 7.0 ma slew rate sr r l = 2 k ? , c l = 50 pf 18 22 v/ s gain bandwidth product gbw (note 2) 4.7 mhz settling time t s 10 v step 0.01% 0.9 1.2 s phase margin 0 0 db gain 55 degree differential input impedance z in 10 12 6 ? pf (@ v s = 15 v, t a = 25 c, unless otherwise noted.) (@ v s = 15 v, t a = 25 c, unless otherwise noted.)
C3C rev. e op249 op249g parameter symbol conditions min typ max unit open loop output resistance r o 35 ? voltage noise e n p-p 0.1 hz to 10 hz 2 v p-p voltage noise density e n f o = 10 hz 75 nv/ hz f o = 100 hz 26 nv/ hz f o = 1 khz 17 nv/ hz f o = 10 khz 16 nv/ hz current noise density i n f o = 1 khz 0.003 pa/ hz voltage supply range v s 4.5 15 18 v notes 1 guaranteed by cmr test. 2 guaranteed by design. specifications subject to change without notice. electrical characteristics op249a op249f parameter symbol conditions min typ max min typ max unit offset voltage v os 0.12 1.0 0.5 1.1 mv offset voltage temperature coefficient tcv os 1 5 2.2 6 v/ c input bias current i b (note 1) 4 20 0.3 4.0 na input offset current i os (note 1) 0.04 4 0.02 1.2 na input voltage range ivr (note 2) 12.5 12.5 v 11 11 v C12.5 C12.5 v common-mode rejection cmr v cm = 11 v 76 110 80 90 db power-supply rejection ratio psrr v s = 4.5 v to 18 v 5 50 7 100 v/v large-signal voltage gain a vo r l = 2 k ? ; v o = 10 v 500 1400 250 1200 v/mv output voltage swing v o r l = 2 k ? 12.5 12.5 v 12 12 v C12.5 C12.5 v short-circuit current limit i sc output shorted to ground 10 60 18 60 ma supply current i sy no load, v o = 0 v 5.6 7.0 5.6 7.0 ma notes 1 t j = 85 c for f grades; t j = 125 c for a grade. 2 guaranteed by cmr test. specifications subject to change without notice. (@ v s = 15 v, ?0 c t a +85 c for f grades and ?5 c t a +125 c for a grade unless otherwise noted.) electrical characteristics op249g parameter symbol conditions min typ max unit offset voltage v os 1.0 3.6 mv offset voltage temperature coefficient tcv os 625 v/ c input bias current i b (note 1) 0.5 4.5 na input offset current i os (note 1) 0.04 1.5 na input voltage range ivr (note 2) 12.5 v 11 v C12.5 v common-mode rejection cmr v cm = 11 v 76 95 db power-supply rejection ratio psrr v s = 4.5 v to 18 v 10 100 v/v large-signal voltage gain a vo r l = 2 k ? ; v o = 10 v 250 1200 v/mv output voltage swing v o r l = 2 k ? 12.5 v 12.0 v C12.5 v short-circuit current limit i sc output shorted to ground 18 60 ma supply current i sy no load, v o = 0 v 5.6 7.0 ma notes 1 t j = 85 c. 2 guaranteed by cmr test. specifications subject to change without notice. (@ v s = 15 v, ?0 c t a +85 c for unless otherwise noted.)
op249 C4C rev. e absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v input voltage 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v differential input voltage 2 . . . . . . . . . . . . . . . . . . . . . . . 36 v output short-circuit duration . . . . . . . . . . . . . . . . indefinite storage temperature range . . . . . . . . . . . . C65 c to +175 c operating temperature range op249a (z) . . . . . . . . . . . . . . . . . . . . . . . C55 c to +125 c op249e, f (z) . . . . . . . . . . . . . . . . . . . . . C40 c to +85 c op249g (p, s) . . . . . . . . . . . . . . . . . . . . . C40 c to +85 c junction temperature op249 (z) . . . . . . . . . . . . . . . . . . . . . . . . C65 c to +175 c op249 (p, s) . . . . . . . . . . . . . . . . . . . . . . C65 c to +150 c lead temperature range (soldering, 60 sec) . . . . . . . 300 c ordering guide * model temperature range package descriptions package options op249az C55 c to +125 c 8-lead cerdip q-8 op249fz C40 c to +85 c 8-lead cerdip q-8 op249gp C40 c to +85 c 8-lead plastic dip n-8 op249gs * C40 c to +85 c 8-lead so so-8 op249gs-reel C40 c to +85 c 8-lead so so-8 op249gs-reel7 C40 c to +85 c 8-lead so so-8 notes * for availability and burn-in information on so and plcc packages, contact your local sales office. for military processed devices, please refer to the standard microcircuit drawing (smd) available at www.dscc.dla.mil/programs/milspec/default.asp caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the op249 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device package type ja 3 jc unit 8-lead hermetic dip (z) 134 12 c/w 8-lead plastic dip (p) 96 37 c/w 8-lead so (s) 150 41 c/w notes 1 absolute maximum ratings apply to packaged parts, unless otherwise noted. 2 for supply voltages less than 18 v, the absolute maximum input voltage is equal to the supply voltage. 3 ja is specified for worst-case mounting conditions, i.e., ja is specified for device in socket for cerdip and p-dip packages; ja is specified for device soldered to printed circuit board for so package. smd part number adi equivalent 5962-9151901M2A op249arcmda 5962-9151901mga op249ajmda 5962-9151901mpa op249azmda
op249 C5C rev. e typical performance characteristics frequency hz open-loop gain db 120 1k 100 80 60 40 20 0 20 10k 100k 1m 10m 100m 0 45 90 135 180 225 t a = 25 c v s = 15v r l = 2k m = 55 gain phase phase c tpc 1. open-loop gain, phase vs. frequency frequency hz power supply rejection db 1k 120 100 80 60 40 20 0 10k 100k 1m t a = 25 c v s = 15v 100 10 psrr +psrr tpc 4. power supply rejection vs. frequency capacitive load pf slew rate v/ s 35 30 0 25 t a = 25 c v s = 15v 20 15 10 5 100 200 300 400 500 negative positive tpc 7. slew rate vs. capacitive load temperature c phase margin c 65 60 45 75 55 50 50 25 0 25 50 75 100 125 gain bandwidth product mhz 10 8 2 6 4 v s = 15v gbw m tpc 2. gain bandwidth product, phase margin vs. temperature temperature c slew rate v/ s 28 26 75 24 50 25 0 25 50 75 100 125 v s = 15v r l = 2k c l = 50pf +sr sr 22 20 18 16 tpc 5. slew rate vs. temperature 0.1% settling time ns output step size volts 0 t a = 25 c v s = 15v a vcl = 1 10 200 400 600 800 1000 0.01% 8 6 4 2 0 2 4 6 8 10 0.1% 0.01% tpc 8. settling time vs. step size frequency hz common-mode rejection db 140 1k 120 100 80 60 40 20 0 10k 100k 1m 10m t a = 25 c v s = 15v 100 tpc 3. common-mode rejection vs. frequency differential input voltage volts slew rate v/ s 28 26 0 24 t a = 25 c v s = 15v r l = 2k 22 20 18 16 0.2 0.4 0.6 0.8 1.0 tpc 6. slew rate vs. differential input voltage frequency hz 100 0 100 80 60 40 20 0 t a = 25 c v s = 15v 1k 10k voltage noise density nv hz tpc 9. voltage noise density vs. frequency
op249 C6C rev. e 0.010 20 100 0.001 t a = 25 c v s = 15v v o = 10v p-p r l = 10k a v = 1 1k 10k 20k tpc 10. distortion vs. frequency 0.10 20 100 0.010 t a = 25 c v s = 15v v o = 10v p-p r l = 10k a v = 1 1k 10k 20k tpc 13. distortion vs. frequency +1 v 1 v bandwidth (0.1hz to 10hz) t a = 25 cv s = 15v 500mv 1s tpc 16. low frequency noise 0.010 20 100 0.001 t a = 25 c v s = 15v v o = 10v p-p r l = 2k a v = 1 1k 10k 20k tpc 11. distortion vs. frequency 0.10 20 100 0.010 t a = 25 c v s = 15v v o = 10v p-p r l = 2k a v = 10 1k 10k 20k tpc 14. distortion vs. frequency frequency hz closed-loop gain db 1k 10 0 10 10k 100k 1m 10m t a = 25 c v s = 15v 60 50 40 30 20 20 100m a vcl = 100 a vcl = 5 a vcl = 1 a vcl = 10 tpc 17. closed-loop gain vs. frequency 0.010 20 100 0.001 t a = 25 c v s = 15v v o = 10v p-p r l = 600 a v = 1 1k 10k 20k tpc 12. distortion vs. frequency 0.10 20 100 0.010 t a = 25 c v s = 15v v o = 10v p-p r l = 600 a v = 10 1k 10k 20k tpc 15. distortion vs. frequency frequency hz impedance 1k 10 0 10k 100k 1m 10m t a = 25 c v s = 15v 50 40 30 20 a vcl = 100 a vcl = 1 a vcl = 10 100 456"> 67).
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op249 C7C rev. e frequency hz output voltage v p-p 25 20 15 10 0 1k 30 5 1m 10m op249 ad8512 ad712 tpc 19. output voltage vs. frequency supply voltage volts output voltage swing volts 0 t a = 25 c r l = 2k 20 5 10 15 20 15 10 5 0 5 10 15 20 tpc 22. output voltage swing vs. supply voltage v os v units 600 t a = 25 c v s = 15v 415 op249 (830 op amps) 1k 160 180 140 120 100 80 60 40 20 0 800 200 400 200 0 600 400 800 1k tpc 25. v os distribution (p package) load capacitance pf overshoot % 60 50 40 100 v s = 15v r l = 2k v in = 100mv p-p 30 20 10 0 a vcl = 1 negative edge a vcl = 1 positive edge a vcl = 5 0 200 300 400 500 70 80 90 tpc 20. small overshoot vs. load capacitance temperature c supply current ma v s = 15v no load 5.2 75 5.4 5.6 5.8 6.0 50 25 0 25 50 75 100 125 tpc 23. supply current vs. temperature m v/ c units 2 v s = 15v 40 c to +85 c (830 op amps) 0 240 300 210 180 150 120 90 60 30 0 270 4 6 8 10 12 14 16 18 20 22 24 tpc 26. tcv os distribution (p package) load resistance maximum output swing volts t a = 25 c v s = 15v 14 12 10 8 0 100 10k 16 6 1k +v ohm = | v ohm | 4 2 tpc 21. maximum output voltage vs. load resistance supply voltage volts supply current ma t a = 25 c 5.0 5.2 5.4 5.6 5.8 6.0 0 5 10 15 20 t a = 125 c t a = 55 c tpc 24. supply current vs. supply voltage time after power applied minutes offset voltage v 1 v s = 15v 0 50 20 30 0 24 40 10 35 tpc 27. offset voltage warm-up drift
op249 C8C rev. e 75 100 1k 10k 10 1 50 25 0 25 50 75 100 125 input bias current pa temperature c v s = 15v v cm = 0v tpc 28. input bias current vs. temperature temperature c input offset current pa 75 80 20 0 40 t a = 25 c v cm = 0v 60 50 25 0 25 50 75 100 125 tpc 31. input offset current vs. temperature 15 10 0 10 5051015 bias current pa common-mode voltage volts t a = 25 c v s = 15v 10 1 10 2 10 3 10 4 tpc 29. bias current vs. common-mode voltage temperature c open-loop gain v/mv 75 80 20 0 40 v s = 15v 60 50 25 0 25 50 75 100 125 r l = 2k r l = 10k tpc 32. open-loop gain vs. temperature time after power applied minutes input bias current pa 2 0 50 20 30 0 48 40 10 610 t a = 25 c v s = 15v tpc 30. bias current warm-up drift temperature c short-circuit output current ma 75 80 20 0 40 v s = 15v 60 50 25 0 25 50 75 100 125 sink source tpc 33. short-circuit output cur- rent vs. junction temperature
op249 C9C rev. e +in in v+ v out v figure 4. simplified schematic (1/2 op249) 1/2 op249 3v 5k +18v 18v 3v 5k 1/2 op249 figure 5. burn-in circuit applications information the op249 represents a reliable jfet amplifier design, featur- ing an excellent combination of dc precision and high speed. a rugged output stage provides the ability to drive a 600 ? load and still maintain a clean ac response. the op249 features a large signal response that is more linear and symmetric than previ- ously available jfet input amplifierscompare the op249s large-signal response, as illustrated in figure 6, to other in dus- try standard dual jfet amplifiers. typically, jfet amplifiers stewing performance is simply specified as just a number of volts/ s. there is no discussion on the quality, i.e., linearity, symmetry, etc., of the stewing response. a) op249 b) lt1057 c) ad712 figure 6. large-signal transient response, a v = 1, v in = 20 v p-p, z l = 2 k ? //200 pf, v s = 15 v
op249 C10C rev. e the op249 was carefully designed to provide symmetrically matched slew characteristics in both the negative and positive directions, even when driving a large output load. an amplifiers slewing limitation determines the maximum frequency at which a sinusoidal output can be obtained without significant distortion. it is, however, important to note that the nonsymmetric stewing typical of previously available jfet amplifiers adds a higher series of harmonic energy content to the resulting responseand an additional dc output compo nent. examples of potential problems of nonsymmetric slewing behavior could be in audio amplifier applications, where a natural low distortion sound quality is desired, and in servo or signal processing systems where a net dc offset cannot be tolerated. the linear and symmetric stewing feature of the op249 makes it an ideal choice for applications that will exceed the full-power bandwidth range of the amplifier. figure 7. small-signal transient response, a v = 1, z l = 2 k ? 100 pf, no compensation, v s = 15 v as with most jfet-input amplifiers, the output of the op249 may undergo phase inversion if either input exceeds the speci- fied input voltage range. phase inversion will not damage the amplifier, nor will it cause an internal latch-up condition. supply decoupling should be used to overcome inductance and resistance associated with supply lines to the amplifier. a 0.1 f and a 10 f capacitor should be placed between each supply pin and ground. open-loop gain linearity the op249 has b oth an extremely high open-loop gain of 1 kv/mv minimum and constant gain linearity. this feature of the op249 enhances its dc precision, and provides superb accu- racy in high closed-loop gain applications. figure 8 illustrates the typical open-loop gain linearityhigh gain accuracy is as sured, even when driving a 600 ? load. offset voltage adjustment the inherent low offset voltage of the op249 will make offset adjustments unnecessary in most applications. however, where a lower offset error is required, balancing can be performed with simple external circuitry, as illustrated in figures 9 and 10. vertical 50 v/div input variation horizontal 5v/div output charge figure 8. open-loop gain linearity. variation in open- loop gain results in errors in high closed-loop gain circuits. r l = 600 ? , v s = 15 v 1/2 op249 v +v v in r3 r1 200k r5 50k r2 31 v out r4 v os adjust range = v r2 r1 figure 9. offset adjust for inverting amplifier configuration 1/2 op249 v +v v in r1 200k r3 50k r2 33 v out r5 v os adjust range = v r2 r1 1 + r5 r4 if r2 << r4 v out v in gain = = 1 + r5 r4 + r2 r4 figure 10. offset adjust for noninverting amplifier configuration in figure 9, the offset adjustment is made by supplying a small voltage at the noninverting input of the amplifier. resistors r1 and r2 attenuates the pot voltage, providing a 2.5 mv (with v s = 15 v) adjustment range, referred to the input. figure 10 illustrates offset adjust for the noninverting amplifier configura- tion, also providing a 2.5 mv adjustment range. as indicated in the equations in figure 10, if r4 is not much greater than r2, there will be a resulting closed-loop gain error that must be accounted for.
op249 C11C rev. e settling time settling time is the time between when the input signal begins to change and when the output permanently enters a prescribed error band. the error bands on the output are 5 mv and 0.5 mv, respectively, for 0.1% and 0.01% accuracy. figure 11 illustrates the op249s typical settling time of 870 ns. moreover, problems in settling response, such as thermal tails and long-term ringing are nonexistent. 10 0% 100 90 500ns 10mv 870ns figure 11. settling characteristics of the op249 to 0.01% reference or v in v out +15v 15v pm7545 db 11 db 0 12 500 c 33pf 75 v dd 0.1 f 0.1 f out 1 agnd v ref 1/2 op249 0.1 f dgnd r fb v dd data input a. unipolar operation reference or v in v out 1/2 op249 +15v pm7545 500 c 33pf 75 out 1 agnd v ref r fb 15v 0.1 f r4 20k 1% r5 10k 1% r3 10k 1% 0.1 f 1/2 op249 dgnd db 11 db 0 12 data input v dd 0.1 f v dd b. bipolar operation figure 12. fast settling and low offset error of the op249 enhances cmos dac performance dac output amplifier unity-gain stability, a low offset voltage of 300 v typical, and a fast settling time of 870 ns to 0.01%, makes the op249 an ideal amplifier for fast digital-to-analog converters. for cmos dac applications, the low offset voltage of the op249 results in excellent linearity performance. cmos dacs, such as the pm-7545, will typically have a code-dependent output resistance variation between 11 k ? and 33 k ? . the change in output resistance, in conjunction with the 11 k ? feedback resistor, will result in a noise gain change. this causes variations in the offset error, increasing linearity errors. the op249 features low offset voltage error, minimizing this effect and maintaining 12-bit linearity performance over the full-scale range of the converter. since the dacs output capacitance appears at the operational amplifiers inputs, it is essential that the amplifier is adequately compensated. compensation will increase the phase margin, and ensure an optimal overall settling response. the required lead compensation is achieved with capacitor c in figure 12.
op249 C12C rev. e figure 13 illustrates the effect of altering the compensation on the output response of the circuit in figure 12a. compensation is required to address the combined effect of the dacs output capacitance, the op amps input capacitance and any stray cap aci- tance. slight adjustments to the compensation capacitor may be required to optimize settling response for any given application. the settling time of the combination of the current output dac and the op amp can be approximated by: t s total = ( t s dac ) 2 + ( t s amp ) 2 the actual overall settling time is affected by the noise gain of the amplifier, the applied compensation, and the equivalent input capacitance at the amplifiers input. discussion on driving a/d converters settling characteristics of operational amplifiers also include an amplifiers ability to recover, i.e., settle, from a transient current output load condition. an example of this includes an op amp driving the input from a sar type a/d converter. although the comparison point of the converter is usually diode clamped, the input swing of plus-and-minus a diode drop still gives rise to a significant modulation of input current. if the closed-loop output impedance is low enough and bandwidth of the amplifier is sufficiently large, the output will settle before the converter makes a comparison decision which will prevent linearity errors or missing codes. figure 14 shows a settling measurement circuit for evaluating recovery from an output current transient. an output disturbing current generator provides the transient change in output load current of 1 ma. as seen in figure 15, the op249 has extremely fast recovery of 274 ns (to 0.01%), for a 1 ma load transient. the performance makes it an ideal amplifier for data acquisition systems. b a c = 5pf response is grossly underdamped, and exhibits ringing c = 15pf fast rise time characteristics, but at expense of slight peaking in response figure 13. effect of altering compensation from circuit in figure 12apm7545 cmos dac with 1/2 op249, unipolar operation. critically damped response will be obtained with c 33 pf. |v ref | 1k i out = 1/2 op249 +15v 15v 0.1 f 0.1 f +15v 1.5k 1n4148 0.1 f 220 1.8k 1k 2n3904 1k 10 f v ref 0.47 f 0.01 f * * * note: decouple close together on ground plane with short lead lengths ttl input +15v 2n2907 7a13 plug-in 7a13 plug-in 300pf figure 14. transient output impedance test fixture the combination of high speed and excellent dc performance of the op249 makes it an ideal amplifier for 12-bit data acquisition systems. examining the circuit in figure 16, one amplifier in the op249 provides a stable C5 v reference voltage for the v ref input of the adc912. the other amplifier in the op249 performs high speed buffering of the a/ds input. examining the worst case transient voltage error (figure 17) at the analog in node of the a/d converter: the op249 recovers in less than 100 ns. the fast recovery is due to both the op249s wide bandwidth and low dc output impedance.
op249 C13C rev. e figure 15. op249s transient recovery time from a 1 ma load transient to 0.01% 1/2 op249 +15v 15v 0.1 f 0.1 f agnd v ref in analog input analog in dgnd hben cs busy clk in adc912 rd 10 f||0.1 f 10 f||0.1 f +5v 15v 1/2 op249 +15v 5v 0.1 f 0.1 f 10 10 f||0.1 f ref02 gnd in out figure 16. op249 dual amplifiers provide both stable C5 v reference input, and buffers input to adc912 figure 17. worst-case transient voltage, at analog in, occurs at the half-scale point of the a/d. op249 buffers the a/d input from figure 16, and recovers in less than 100 ns.
op249 C14C rev. e 99 i1 v2 4 7 i os c in 3 j1 j2 e os r3 r4 c2 5 6 50 2 in in+ r1 r2 v3 10 d2 d1 8 9 r5 c3 c4 r6 g3 g4 r8 r7 13 c6 c5 12 r9 r10 g6 g5 r11 r12 r13 r14 l2 l1 g1 g2 1 14 15 16 g7 99 17 g8 c9 r15 r16 c10 c11 r17 r18 c12 g11 18 19 20 l3 g12 c13 c14 g13 g14 r22 r21 r20 r19 g9 g10 21 22 l4 50 50 99 g15 g16 r23 r24 c15 c16 r26 r25 24 23 25 26 d3 d4 d7 d8 g17 g18 r27 r28 l5 30 29 d5 d6 v out g19 g20 27 28 + + v4 v5 figure 18. macro-model op249 spice macro-model figures 18 and table i show the node and net list for a spice macromodel of the op249 the model is a simplified version of the actual device and simulates important dc parameters such as v os , i os , i b , a vo , cmr, v o and i sy . ac parameters such as slew rate, gain and phase response and cmr change with frequency are also simulated by the model. the model uses typical parameters for the op249. the poles and zeros in the model were determined from the actual open and closed-loop gain and phase response of the op249. in this way, the model presents an accurate ac representation of the actual device. the model assumes an ambient temperature of 25 c.
op249 C15C rev. e op249 macro-model ?subckt op249 1 2 30 99 50 * input stage & pole at 100mhz * r1 2 3 5e11 r2 1 3 5e11 r3 5 50 652.3 r4 6 50 652.3 cin 1 2 5e-12 c2 5 6 1.22e-12 i1 99 4 1e-3 ios 1 2 3.1e-12 eos 7 1 poly(1) 20 24 150e-6 1 j1 5 2 4 jx j2 6 7 4 jx * * second stage & pole at 12.2hz * r5 9 99 326.1e6 r6 9 50 326.1e6 c3 9 99 40e-12 c4 9 50 40e-12 g1 99 9 poly(1) 5 6 4.25e-3 1.533e-3 g2 9 50 poly(1) 6 5 4.25e-3 1.533e-3 v2 99 8 2.9 v3 10 50 2.9 d1 9 8 dx d2 10 9 dx * * pole-zero pair at 2mhz/4.0mhz * r7 11 99 1e6 r8 11 50 1e6 r9 11 12 1e6 r10 11 13 1e6 c5 12 99 37.79e-15 c6 13 50 37.79e-15 g3 99 11 9 24 1e-6 g4 11 50 24 9 1e-6 * * zero-pole pair at 4mhz/8mhz * r11 99 15 ie6 r12 14 15 1e6 r13 14 16 1e6 r14 50 16 1e6 i1 99 15 19.89e-3 i2 50 16 19.89e-3 g5 99 14 11 24 1e-6 g6 14 50 24 11 1e-6 * * pole at 20mhz * r15 17 99 1e6 r16 17 50 1e6 c9 17 99 7.96e-15 c10 17 50 7.96e-15 g7 99 17 14 24 1e-6 g8 17 50 24 14 1e-6 * * pole at 50mhz * r17 18 99 1e6 r18 18 50 1e6 c11 18 99 3.18e-15 c12 18 50 3.18e-15 g9 99 18 17 24 1e-6 g10 18 50 24 17 1e-6 table i. spice net list * * pole at 50mhz * r19 19 99 1e6 r20 19 50 1e6 c13 19 99 3.18e-15 c14 19 50 3.18e-15 g11 99 19 18 24 1e-6 g12 19 50 24 18 1e-6 * * common-mode gain network with zero at 60khz * r21 20 21 1e6 r22 20 22 1e6 i3 21 99 2.65 i4 22 50 2.65 g13 99 20 3 24 1.78e-11 g14 20 50 24 3 1.78e-11 * * pole at 50mhz * r23 23 99 1e6 r24 23 50 1e6 c15 23 99 3.18e-15 c16 23 50 3.18e-15 g15 99 23 19 24 1e-6 g16 23 50 24 19 1e-6 * * output stage * r25 24 99 135e3 r26 24 50 135e3 r27 29 99 70 r28 29 50 70 i5 29 30 4e-7 g17 27 50 23 29 14.3e-3 g18 28 50 29 23 14.3e-3 g19 29 99 99 23 14.3e-3 g20 50 29 23 50 14.3e-3 v4 25 29 .4 v5 29 26 .4 d3 23 25 dx d4 26 23 dx d5 99 27 dx d6 99 28 dx d7 50 27 dy d8 50 28 dy * models used * ?model jx pjf(beta=1.175e-3 vto=?.000 is=21e-12) ?model dx d(is=1e-15) ?model dy d(is=1e-15 bv=50) ?ends op249 * * pspice is a registered trademark of microsim corporation. ** hspice is a tradename of meta-software, inc.
C16C c00296aC0C1/02(e) printed in u.s.a. op249 8-lead cerdip (q-8) 8 1 4 5 0.310 (7.87) 0.220 (5.59) pin 1 0.005 (0.13) min 0.055 (1.4) max seating plane 0.023 (0.58) 0.014 (0.36) 0.200 (5.08) max 0.150 (3.81) min 0.070 (1.78) 0.030 (0.76) 0.200 (5.08) 0.125 (3.18) 0.100 (2.54) bsc 0.060 (1.52) 0.015 (0.38) 0.405 (10.29) max 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) outline dimensions dimensions shown in inches and (mm). 8-lead plastic dip (n-8) 8 14 5 0.430 (10.92) 0.348 (8.84) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 8-lead narrow body (soic) (so-8) 0.1968 (5.00) 0.1890 (4.80) 8 5 4 1 0.2440 (6.20) 0.2284 (5.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.0688 (1.75) 0.0532 (1.35) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45 revision history location page 9/01 data sheet changed from rev. d to rev. e. edits to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edits to pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edits to electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2, 3 edits to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 edits to package type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 edits to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 deleted wafer test limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 deleted dice characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 edits to typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 edits to macro-model figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 edits to outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

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